1. Field of the Invention
The present invention relates to a wiring board on which semiconductor devices and various other types of devices are mounted, to a method for manufacturing the same, and to a semiconductor package that uses the wiring board.
2. Description of the Related Art
Due to recent advances in the performance and functionality of semiconductor devices, the number of terminals is increasing, the terminals are being spaced apart at a narrower pitch, and processing speed is also increasing. This has led to increased demand for higher-density wiring and higher speed in wiring boards for packaging on which a semiconductor device is mounted. A built-up printed board that is a type of multilayer wiring board is an example of the conventional wiring board for packaging that is commonly used.
FIG. 1 is a sectional view showing the conventional built-up printed board in general use. In the conventional built-up printed board 70 shown in FIG. 1, a base core board 73 composed of glass epoxy is provided, and a penetrating through-hole 71 having a diameter of approximately 300 μm is formed in this base core board 73 by drilling. Conductor wiring 72 is also formed on both faces of the base core board 73, and an interlayer insulating film 75 is provided so as to cover the conductor wiring 72. A via hole 74 is formed in the interlayer insulating film 75 so as to connect to the conductor wiring 72, and conductor wiring 76 is provided on the interlayer insulating film 75 so as to connect to the conductor wiring 72 through the via hole 74. The board is also provided with multilayer wiring as needed by repeatedly forming conductor wiring and an interlayer insulating film in which a via hole is formed to the conductor wiring 76.
However, this built-up printed board 70 has problems in that the use of a glass epoxy printed board in the base core board 73 makes the heat resistance inadequate, and the heat treatment performed in order to form the interlayer insulating film 75 causes shrinkage, warping, swelling, and other deformation of the base core board 73. As a result, in the step for exposing the resist when the semiconductor layer (not shown in the drawing) is patterned and the conductor wiring 76 is formed, the positional accuracy of the exposure is significantly reduced, making it difficult to form a high-density fine-pitch wiring pattern on the interlayer insulating film 75. In order for the penetrating through-hole 71 and the conductor wiring 72 to be reliably connected to each other, a land must be provided to the portion of the conductor wiring 72 that connects to the penetrating through-hole 71. Even when a wiring design adapted for increased speed is adopted in a built-up layer composed of an interlayer insulating film 75 and conductor wiring 76, the presence of the land and the thick penetrating through-hole makes impedance difficult to control, and leads to a large loop inductance. Problems therefore occur in that the operating speed of the built-up printed board as a whole decreases, and the built-up printed board is difficult to adapt for increased speed in a semiconductor device.
Methods for manufacturing a printed board have been proposed to replace the method whereby a drill is used to form a penetrating through-hole in a glass epoxy board. These methods are designed to overcome the types of problems caused by the penetrating through-hole in the built-up printed board (for example, Japanese Laid-open Patent Application No. 2000-269647, and Oyama T. (and three others), “Package Having All-layer Fine-pitch IVH,” October 2001, Proceedings of the 11th Microelectronics Symposium, pp. 131-134).
FIGS. 2A through 2C are sectional views showing the sequence of steps in the method for manufacturing the built-up printed board disclosed in Japanese Laid-open Patent Application No. 2000-269647. In the conventional method for manufacturing a built-up printed board described in the abovementioned publication, a prepreg 82 is prepared in which a prescribed conductor wiring 81 is formed on the surface, as shown in FIG. 2A. A through-hole 83 having a diameter of 150 to 200 μm is then formed in the prepreg 82 by laser machining. The through-hole 83 is then filled with a conductor paste 84, as shown in FIG. 2B. Then, as shown in FIG. 2C, a plurality of such prepregs 82 are created; specifically, a plurality of prepregs 82 are created in which a through-hole 83 is formed, the through-hole 83 is filled with a conductor paste 84, and the prepregs are layered together. At this time, the land pattern 86 in the conductor wiring 81 is connected to the through-hole 83 of the adjacent prepreg. A built-up printed board 85 that does not have any penetrating through-holes can thereby be created.
However, this conventional technique has problems in that the positional accuracy during layering of the prepregs 82 is low, and it is difficult to reduce the diameter of the land pattern 86. It is therefore difficult to increase the density of the wiring, and the enhancement of impedance control and reduction of loop inductance are inadequate. Furthermore, since the process temperature during layering is limited by the prepreg material, this technique also has problems in that the through-hole connections have poor reliability after layering.
In order to overcome the problems of the conventional wiring board described above, the inventors, et al. have proposed a method for fabricating a wiring board by forming a wiring layer on a metal board or other support body, and then removing a portion of the support body (see Japanese Laid-open Patent Application No. 2002-198462 (pp. 8, 11, and FIG. 17)). FIGS. 3A and 3B are sectional views showing the sequence of steps in the method for manufacturing a wiring board disclosed in Japanese Laid-open Patent Application No. 2002-198462. In the conventional method for manufacturing a wiring board according to this publication, a carrier board 91 composed of a metal board or the like is prepared, as shown in FIG. 3A. Conductor wiring 92 is then formed on this carrier board 91, an interlayer insulating film 93 is formed so as to cover the conductor wiring 92, and a via hole 94 is formed in this interlayer insulating film 93 so as to be connected to the conductor wiring 92. Conductor wiring 95 is then formed on the interlayer insulating film 93. The conductor wiring 95 is formed so as to be connected to the conductor wiring 92 through the via hole 94. The board is also provided with multilayer wiring as needed by repeating the steps for forming the interlayer insulating film 93, the via hole 94, and the conductor wiring 95. Then, as shown in FIG. 3B, a portion of the carrier board 91 is removed by etching, the conductor wiring 92 is exposed, and a support body 96 is formed. A wiring board 97 is thereby manufactured.
According to this technique disclosed in Japanese Laid-open Patent Application No. 2002-198462, the wiring board 97 has no penetrating through-holes at all, eliminating the above-described problems caused by the penetrating through-hole, and allowing a high-speed wiring design to be created. A metal board or the like having excellent heat resistance is also used as the carrier board 91. Therefore, there is no shrinking, warping, swelling, or other deformation such as when a glass epoxy board is used, and higher-density fine-pitch wiring can be created. A wiring board having high strength can also be obtained by specifying the mechanical characteristics of the interlayer insulating film 93 as described above.
However, the aforementioned conventional technique has the problems described below. Semiconductor devices are mounted at high density in conjunction with recent remarkable advances in performance and multi-function capability in mobile devices and the like. A technique called system-in-package (SiP) has recently gained attention as a technique for implementing a plurality of semiconductor devices on a single wiring board. In order to obtain increased reliability in this SiP-type semiconductor package using a conventional wiring board, it is preferred that the via diameter, which is the contact surface between the upper and lower wiring and the via, be increased as much as possible, that electrical conduction be maintained, and that the mechanical bonding strength of the wiring be enhanced. However, when the via diameter is increased, the diameter of the land that is in contact with the via must also be increased for reasons relating to the alignment precision in the manufacturing steps. When, for example, the minimum line width of the wiring is set, problems occur in that the number of wires running between lands decreases, and setbacks occur in the process of increasing the wiring density. Moreover, the via diameter and the land diameter of wiring boards tend to decrease each year in conjunction with increased multifunction capability in semiconductor devices, which is less favorable for the reliability of wiring connections.
Photo vias and laser vias are two types of via holes commonly formed in wiring boards. A photo via is patterned by a process in which a photosensitive resin is used as an interlayer insulating film, the photosensitive resin is irradiated with ultraviolet rays through a glass mask, and exposure and development are performed. A laser via is formed by using laser ablation to thermally remove the interlayer insulating film that corresponds to the via portion. In either case, the usual process produces a via opening that has a cylindrical shape or a conical shape in which the diameter of the opening is larger on the light-exposed surface or the laser-irradiated surface. However, this type of cylindrical or conical via shape has problems in that thermal stress occurs between the wiring material and the insulating resin, which have different thermal expansion coefficients, during the heat cycle test that is one of the reliability tests. As a result, interface peeling of Cu as a typical wiring conductor occurs at the interface between the via and the wiring, and particularly at the interface between the lower-layer wiring and the bottom of a via having a small-diameter opening, and an open-circuit failure occurs. This defect becomes particularly severe in a micro-via in which the diameter of the opening at the bottom of the via is less than 80 μm, and the aspect ratio calculated based on the diameter of the opening at the bottom of the via and the thickness of the insulating resin is 1 or higher.
These problems are caused by the difference in thermal expansion coefficient between the wiring material and the insulating resin, as previously mentioned. Another contributing factor is the small surface area of contact between the conductor in the via and the interlayer insulating film on the lateral face of the via. Problems also occur when the wiring board is abruptly subjected to an excessive acceleration, such as in a drop impact test, in that peeling occurs in the bottom portion of the via where the bonding strength is low. The reason for this is that when the via shape is cylindrical or conical, it is difficult in terms of shape to prevent the via conductor from peeling off and separating from the via bottom when an outside force is exerted in the direction from the via bottom, where the opening diameter is small, to the via top, where the opening diameter is large.
Compared to a common conventional built-up board provided with a thick core member having a penetrating through-hole, these problems are especially severe in a novel coreless-type wiring board in which a core member is not provided, such as the wiring boards disclosed in Japanese Laid-open Patent Application No. 2002-198462 and Oyama T. (and three others), “Package Having All-layer Fine-pitch IVH,” Oct. 2001, Proceedings of the 11th Microelectronics Symposium, pp. 131-134, due to the board's extremely thin profile. In the common conventional built-up board, the thickness of the core member makes the board sturdy, and almost no warping occurs. However, warping easily occurs in a coreless-type conventional wiring board due to the temperature history of the heat treatment step during board manufacturing and due to the vertically asymmetrical structure of the wiring board. Concentration of stress at the bottom of the via is also sometimes accelerated depending on the shape of the warp.